Addressing the challenges of autonomous driving: Page 2 of 4

November 05, 2018 // By Willard Tu
One of the hottest topics within the automotive world at the moment is autonomous driving, and both existing automotive manufacturers and new entrants to the automotive market are developing vehicles which have autonomous capability. These developers of autonomous capability are benefiting from Moore’s law, which has enabled significant increases in processing capability and sensor technology while also lowering the cost. Willard Tu

Architecture

At the heart of implementing an autonomous capability is the centralised processing module. To successfully implement autonomous capability, the centralised processing module must contain the following functions:

  • Data aggregation, pre-processing and distribution (DAPD) – This interfaces with the different sensor modalities performing basic processing, routing and switching of information between processing units and accelerators within the processing unit.
  • High performance serial processing – High performance processing element which performs data extraction, sensor fusion and high level decision-making based upon its inputs. In some applications, neural networks will be implemented within the high performance serial processing.
  • Safety processing – Performing real time processing and vehicle control based upon the detected environment provided by pre-processing in the DAPD device and results from the neural network acceleration and high performance serial processing elements.


Architecture of the centralised processing module.

The creation of a centralised processing module presents the designer with several interfacing, scalability, compliance and performance challenges, along with the traditional Size, Weight and Power – Cost (SWaP-C) , challenges when deployed in a power and thermally constrained environment. These SWaP-C challenges are particularly apparent when addressing the DAPD and Safety Processors.

 

Addressing the Challenges

One solution to these challenges is to use a single device which can provide not only the interfacing, pre-processing and routing capabilities of the DAPD but is also capable of including safety processing and potentially neural network acceleration within the same silicon. This highly integrated approach enables a tightly integrated solution benefiting the SWaP-C significantly.

Such a highly integrated solution is possible using the Xilinx Automotive Grade Zynq UltraScale+ MPSoC heterogeneous system on chip. This range of devices provides programmable logic coupled with four high performance ARM A53 cores, forming a tightly integrated processing unit. For real-time control, the Zynq UltraScale+ MPSoC also provides a real-time processing unit (RPU) which contains lockstep dual ARM R5 processors capable of implementing safety features up to ASIL C and intended for safety-critical applications. To provide the necessary functional safety, the RPU has been designed with the ability to reduce, detect and mitigate single random failures including both hardware and single event induced. These devices enable efficient segmentation of the functionality between the processor system resources and the programmable logic.

Design category: 

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.