Another challenge is implementing the safety processors. These must act upon commands received from the DAPD and high performance serial processing. These commands enable the safe navigation of the vehicle within its environment. The safety processors are required to interact directly with vehicle controls such as steering, acceleration and braking. This is a critical aspect of autonomous driving as errors here can result in the loss of life or damage to the environment. The Xilinx automotive grade Zynq UltraScale+ MPSoC contains dual lockstep ARM R5 cores within a Real-time Processing Unit (RPU) which can be used to implement the safety processing.
Along with the lockstep capability of the RPU cores, several additional mitigation provisions have also been implemented. This includes the introduction of Error Correction Codes for the RPU tightly coupled memories and the caches, while the DDR memory is protected with Double Error Detection Single Error Correction codes. The inclusion of ECC on caches and memories ensures the integrity of both the application programme and data required to implement the autonomous vehicle control. To ensure the underlying hardware has no faults prior to operation there is also provision for Built-in Self-Test (BIST) during power on. Additional BIST can also be executed at the request of the user during operation as required. The architecture of the Zynq UltraScale+ MPSoC also provides the ability to implement functional isolation of memory and peripherals within the device.
The inclusion of these facilities within the Xilinx automotive grade Zynq UltraScale+ MPSoC, enables the safety processing to be implemented within the same silicon as the DAPD and potentially Neural Network Acceleration. To ensure industry-leading device quality, Xilinx has gathered industry requirements and merged those into an internal quality control programme called Beyond-AEC-Q100. Doubling most of the testing requirements within this framework, Xilinx ensures a healthy safety margin for its automotive devices. Of course, higher integration also reduces the complexity of the PCB design and interconnect required in the final solution while offering a lower power dissipation. Conclusion
The provision of autonomous driving capability requires the implementation of a centralised processing module which faces SWaP-C challenges. A highly integrated solution based on using Xilinx automotive grade Zynq UltraScale+ MPSoC for the DAPD, Neural Network Accelerator and Safety Processor enables the creation of a smaller, lower weight and more power-efficient solution.
About the author:
Willard Tu is Sr Director Automotive Market at Xilinx – www.xilinx.com